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TM
HA-5320/883
High Speed Precision Sample and Hold Amplifier
Description
The HA-5320/883 was designed for use in precision, high speed data acquisition systems. The circuit consists of an input transconductance amplifier capable of providing large amounts of charging current, a low leakage analog switch, and an output integrating amplifier. The analog switch sees virtual ground as its load; therefore, charge injection on the hold capacitor is constant over the entire input/ output voltage range. The pedestal voltage resulting from this charge injection can be adjusted to zero by use of the offset adjust inputs. The device includes a hold capacitor. However, if improved droop rate is required at the expense of acquisition time, additional hold capacitance may be added externally. This monolithic device is manufactured using the Intersil Dielectric Isolation Process, minimizing stray capacitance and eliminating SCR's. This allows higher speed and latch-free operation. For further information, please see Application Note AN538.
April 2002
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Gain, DC . . . . . . . . . . . . . . . . . . . . . . . . 2 x 106 V/V (Typ) * Acquisition Time . . . . . . . . . . . . . . . 1.0s (0.01%) (Typ) * Droop Rate . . . . . . . . . . . . . . . . 0.08V/s (+25oC) (Typ) 17V/s (Full Temperature) (Typ) * Aperture Time . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Typ) * Hold Step Error . . . . . . . . . . . . . . . . . . . . . . 1.0mV (Typ) * Internal Hold Capacitor * Fully Differential Input * TTL Compatible
Applications
* * * * * High Bandwidth Precision Data Acquisition Systems Inertial Navigation and Guidance Systems Ultrasonics SONAR / RADAR Digital to Analog Converter Deglitcher
Pinout
HA-5320/883 (CERDIP) TOP VIEW
-INPUT 1 +INPUT 2 OFFSET ADJ 3 OFFSET ADJ 4 V- 5 SIG GND 6 OUTPUT 7 14 S/H CONTROL 13 SUPPLY GND 12 NC 11 CEXT 10 NC 9 V+ 8 INT. BW
Ordering Information
PART NUMBER HA1-5320/883 TEMPERATURE RANGE -55oC to +125oC PACKAGE 14 Lead CerDIP
Functional Diagram
OFFSET ADJUST 3 4 V+ 9
HA-5320/883 -INPUT 1 +INPUT 2
100pF
+
-
7 OUTPUT
S/H CONTROL 14
13 SUPPLY GND
5 V-
6 SIG GND 11 CEXT
8 INTEGRATOR BANDWIDTH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
Spec Number
511096-883
FN2927.4
HA-5320/883
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage (S/H Pin) . . . . . . . . . . . . . . . . . . . . . +8V, -15V Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . . . . . . 20mA Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Thermal Information
Thermal Resistance JA JC CerDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W 20oC/W Package Power Dissipation at +75oC CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Package Power Dissipation Derating Factor Above +75oC CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mW/oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . .-55oC TA +125oC Operating Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Logic Level Low (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic Level High (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 5.0V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 100pF; Signal GND = Supply GND, Unless Otherwise Specified GROUP A SUBGROUP 1 2, 3 Input Bias Current +IB 1 2, 3 -IB 1 2, 3 Input Offset Current IIO 1 2, 3 Open Loop Voltage Gain +AVS RL = 1k, VOUT = +10V 1 2, 3 -AVS RL = 1k, VOUT = -10V 1 2, 3 Common Mode Rejection Ratio +CMRR V+ = 10V, V- = -20V, VOUT = -5V, VS/H = -4.2V, VGND = -5V V+ = 20V, V- = -10V, VOUT = +5V, VS/H = 5.8V, VGND = +5V VOUT = +10V 1 2, 3 1 2, 3 1 2, 3 -IO VOUT = -10V 1 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN -1 -2 -200 -200 -200 -200 -100 -100 120 110 120 110 80 80 80 80 10 10 -10 -10 MAX +1 +2 +200 +200 +200 +200 +100 +100 UNITS mV mV nA nA nA nA nA nA dB dB dB dB dB dB dB dB mA mA mA mA
PARAMETERS Input Offset Voltage
SYMBOL VIO
CONDITIONS
-CMRR
Output Current
+IO
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
Spec Number
511096-883
2
HA-5320/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 100pF; Signal GND = Supply GND, Unless Otherwise Specified GROUP A SUBGROUP 1 2, 3 -VOP RL = 1k 1 2, 3 Power Supply Current +ICC VOUT = 0V, IOUT = 0mA 1 2, 3 -ICC VOUT = 0V, IOUT = 0mA 1 2, 3 Power Supply Rejection Ratio +PSRR V+ = 14.5V, 15.5V V- = -15V, -15V V+ = +15V, +15V, V- = -14.5V, -15.5V VIN = 0V 1 2, 3 1 2, 3 1 2, 3 IINH VIN = 5V 1 2, 3 Digital Input Voltage VIL 1 2, 3 VIH 1 2, 3 Output Voltage Droop Rate NOTE: 1. Internal power dissipation may limit output current below 20mA. VD VOUT = 0V 2 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +125oC MIN 10 10 -13 -13 80 80 65 65 2.0 2.0 MAX -10 -10 13 13 4 10 0.1 0.1 0.8 0.8 100 UNITS V V V V mA mA mA mA dB dB dB dB A A A A V V V V V/s
PARAMETERS Output Voltage Swing
SYMBOL +VOP
CONDITIONS RL = 1k
-PSRR
Digital Input Current
IINL
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. See AC Specifications in Table 3.
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
Spec Number
511096-883
3
HA-5320/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Hold Mode Feedthrough Hold Step Error SYMBOL VHMF VERROR EN(SAMPLE)
CONDITIONS VIN = 10VP-P , 100kHz VIH = 3.5V, VIL = 0V, TRISE (VIL to VIH) = 10ns DC to 10MHz, VS/H = 0V, RLOAD = 2k DC to 10MHz, VS/H = 5V, RLOAD = 2k VS/H = 0V VS/H = 0V, Delta VIN = 20V CL = 50pF, RL = 2k, VOUT = -5V to +5V Step 10%, 90% pts CL = 50pF, RL = 2k, VOUT = +5V to -5V Step 10%, 90% pts CL = 50pF, RL = 2k, VOUT = 0V to +200mV Step 10%, 90% pts CL = 50pF, RL = 2k, VOUT = 0V to -200mV Step 10%, 90% pts CL = 50pF, RL = 2k, VOUT = 0V to +200mV Step CL = 50pF, RL = 2k, VOUT = 0V to -200mV Step CL = 50pF, RL = 2k, VOUT = 0V to 10V Step
NOTES 1 1
TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC
MIN -11
MAX 3 11
UNITS mV mV
Sample Mode Noise Voltage Hold Mode Noise Voltage Input Capacitance Input Resistance Slew Rate
1
-
200
VRMS VRMS pF M V/s
EN(HOLD) CIN RIN +SR
1
-
200
1 1 1
1 30
5 -
-SR
1
+25oC
30
-
V/s
Rise and Fall Times
TR
1
+25oC
-
150
ns
TF
1
+25oC
-
150
ns
Overshoot
+OS
1
+25oC +25oC +25oC
-
25
%
-OS
1
-
25
%
0.1% Acquisition Time
TACQ 0.1%
1
-
1.2
s
NOTE: 1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.
TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA. SUBGROUPS (SEE TABLE 1) 1(Note 1), 2, 3 1, 2, 3 1
Spec Number 4
511096-883
HA-5320/883 Die Characteristics
DIE DIMENSIONS: 92 x 152 x 19 1mils METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA GLASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA WORST CASE CURRENT DENSITY: 1.742 x 105 A/cm2 TRANSISTOR COUNT: 184 SUBSTRATE POTENTIAL: V-
Metallization Mask Layout
HA-5320/883
SUPPLY GND (13)
CEXT (11)
V+ (9)
S/H CTRL (14) -INPUT (1)
(8) INT BW
(7) OUTPUT
+INPUT (2) (3) VIO ADJ (4) VIO ADJ (5) V-
(6) SIG GND
Spec Number 5
511096-883
HA-5320/883 Burn-In Circuits
HA-5320/883 DIP BURN-IN/LIFE TEST CIRCUIT
1 2 R1 3 4 -V D2 C2 5 6 7
14 13 12 11 10 9 8 C1 D1 +V
NOTES: 1. R1 = 100k, 5%, (per socket). 2. C1, C2 = 0.01F minimum per socket or 0.1F minimum per row. 3. D1, D2 = 1N4002 or equivalent (per board). 4. +V = +15.5V 0.5V, -V = -15.5V 0.5V.
Spec Number 6
511096-883
HA-5320/883 Packaging
c1 -A-DBASE METAL b1 M M (b) SECTION A-A (c) LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD DUAL-IN-LINE FRIT-SEAL CERAMIC PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2 8
E
-Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D -CQ A DS
c1
L
eA
D E e eA eA/2 L Q S1 S2
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
e
DS
eA/2
c
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling Dimension: Inch. 11. Materials: Compliant to MIL-I-38535.
aaa bbb ccc M N
Spec Number 7
511096-883
TM
HA-5320
High Speed Precision Sample and Hold Amplifier
errors. Polystyrene dielectric is a good choice for operating temperatures up to +85oC. Teflon and glass dielectrics offer good performance to +125oC and above. The hold capacitor terminal (pin 11) remains at virtual ground potential. Any PC connection to this terminal should be kept short and "guarded" by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current.
Teflon is a registered Trademark of Dupont Corporation.
DESIGN INFORMATION
May 2002
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Applying the HA-5320
The HA-5320 has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note 517 for a collection of circuit ideas. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01 to 0.1F, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13. The ideal ground connections are pin 6 (SIG. Ground) directly to the system Signal Ground, and pin 13 (Supply Ground) directly to the system Supply Common. Hold Capacitor The HA-5320 includes a 100pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins 7 and 11. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. If an external hold capacitor CEXT is used, then a noise band- width capacitor of value 0.1CEXT should be connected from pin 8 to ground. Exact value and type are not critical. The hold capacitor CEXT should have high insulation resistance and low dielectric absorption, to minimize droop
OFFSET ADJUST 15mV 3 1 VIN S/H CONTROL H S 2 14 HA-5320 13 6 8 -15V +15V 10k CEXT 4 5 9 11 100pF +
Applications
Figure 1 shows the HA-5320 connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a 12-bit accurate output from the converter. The application may call for an external hold capacitor CEXT as shown. As mentioned earlier, 0.1CEXT is then recommended at pin 8 to reduce output noise in the Hold mode. The HA-5320 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/ H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration.
HI-574A 7 13
-
+
-
INPUT DIGITAL OUTPUT
CONVERT R/C ANALOG COMMON
0.1CEXT SYSTEM POWER GROUND SYSTEM SIGNAL GROUND
5 9
FIGURE 1. TYPICAL HA-5320/883 CONNECTIONS; NONINVERTING UNITY GAIN MODE
Spec Number 8
511096-883
HA-5320/883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Test Circuits
CHARGE TRANSFER AND DRIFT CURRENT
1 2 S/H CONTROL INPUT 14
-INPUT +INPUT S/H CONTROL HA-5320
OUTPUT
7 8 11 N.C. N.C.
VO
(CH = 100pF)
CHARGE TRANSFER TEST 1. Observe the "hold step" voltage Vp:
S/H CONTROL VO Vp HOLD (+3.5V) SAMPLE (0V)
DRIFT CURRENT TEST 1. Observe the voltage "droop", VO/T:
S/H CONTROL HOLD (4.0V) SAMPLE (0V)
VO T
VO
2. Compute charge transfer: Q = VpCH 2. Measure the slope of the output during hold, VO /T, and compute drift current: ID = CH VO/T.
HOLD MODE FEED THROUGH ATTENUATION
+V ANALOG MUX OR SWITCH 1 10Vp-p 100kHz SINE WAVE 2 AIN 14 -IN +IN S/H CONTROL SUPPLY CEXT GND S/H CONTROL INPUT 13 TO SUPPLY COMMON 11 N.C. REF COM 6 TO SIGNAL GND INT. COMP. 8 N.C. OUT 7 HA-5320 9 5 VOUT -V
VIN
Feedthrough in dB = 20 Log VOUT = Voltsp-p, Hold Mode, VIN = Voltsp-p.
VOUT where: VIN
Spec Number 9
511096-883
HA-5320/883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Performance Curves
VSUPPLY = 15VDC
DRIFT CURRENT vs TEMPERATURE
TYPICAL SAMPLE AND HOLD PERFORMANCE AS FUNCTION OF HOLDING CAPACITOR
10 5 ACQUISITION TIME FOR 10V STEP TO +0.01%(s)
1000
CH = 100pF, INTERNAL
0.5
IDRIFT (pA)
1.0
VOLTAGE DROOP DURING HOLD MODE (mV/100ms)
100
10
0.1 0.05 SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR (mV) 1000 10K CH VALUE (pF) 100K 1.0
0.01 100
-25 0 +25 +50 +75 +100 +125 TEMPERATURE (oC)
OPEN LOOP GAIN AND PHASE RESPONSE
120 100 80 GAIN (dB) 60 40 20 0 G (CH = 1100pF) 0 45 90 135 180 PHASE (DEGREES)
(CH = 100pF) G
10
100
1K 10K FREQUENCY (Hz)
100K
1M
10M
TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR HOLD STEP vs. INPUT VOLTAGE
HOLD STEP VOLTAGE (mV) TA = +25oC 1.0 0.1 0.01 CH = 100pF CH = 1000pF CH = 0.01F
HOLD STEP vs. LOGIC (VIH) VOLTAGE
2.0 CH = 100pF HOLD STEP VOLTAGE (mV) 1.5
+75oC
1.0 +25oC 0.5
-10
-8
-6
-4
-2
2
4
6
8
10
DC INPUT (V) 0.0 2 3 4 LOGIC LEVEL HIGH (V) 5
Spec Number 10
511096-883
HA-5320/883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Glossary of Terms
Acquisition Time The time required following a "sample" command, for the output to reach its final value within 0.1% or 0.01%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. Charge Transfer The small charge transferred to the holding capacitor from the inter-electrode capacitance of the switch when the unit is switched to the HOLD mode. Charge transfer is directly proportional to sample-to-hold offset pedestal error, where: Charge Transfer (pC) = CH (pF) x Offset Error (V) Aperture Time The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is the interval between the conditions of 10% open and 90% open. Hold Step Error Hold Step Error is the output error due to Charge Transfer (see above). It may be calculated from Charge Transfer, using the following relationship:
HOLD STEP (V) = CHARGE TRANSFER (pC) HOLD CAPACITANCE (pF) See Performance Curves.
Effective Aperture Delay Time (EADT) The difference between propagation time from the analog input to S/H switch, and digital delay time between the Hold command and opening of the switch. EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to VIN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of VIN that occurred before the Hold command. Aperture Uncertainty The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. Drift Current The net leakage current from the hold capacitor during the hold mode. Drift current can be calculated from the droop rate using the formula: ID (pA) = CH (pF) x V T (V/s)
TYPICAL PERFORMANCE CHARACTERISTICS PARAMETER Input Voltage Range Offset Voltage Drift Gain Bandwidth Product (CH = 100pF) Gain Bandwidth Product (CH = 1000pF) Full Power Bandwidth Output Resistance (Hold Mode) 0.1% Acquisition Time 0.01% Acquisition Time Effective Aperture Delay Time Aperture Uncertainty 0.01% Hold Mode Settling Time VO = 10V Step, RL = 2K, CL = 50pF VO = 10V Step, RL = 2K, CL = 50pF Av = +1, VO = 200mVP-P, RL = 2K, CL = 50pF Av = +1, VO = 200mVP-P, RL = 2K, CL = 50pF VO = 20VP-P, RL = 2K, CL = 50pF CONDITIONS TEMPERATURE Full Full +25 C +25 C +25oC +25 C +25oC +25oC +25oC +25 C +25oC
o o o o
TYP 10 5 2 0.18 600 1.0 0.8 1.0 -25 0.3 165
UNITS V V/oC MHz MHz kHz s s ns ns ns
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 11
511096-883

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